1. Field of the Invention
The present invention relates to a negative voltage boosting circuit, particularly relates to a negative voltage boosting circuit using a MOS transistor for a switch for transferring charge.
2. Description of the Prior Art
Recently, electrically writable EEPROM and a flash memory have been used for multiple equipment such as a mobile telephone. In writing or erasing data to/in these memories, negative high voltage is generally required. As it economically increases the cost to mount negative high voltage power supply in equipment separately from a power source that outputs positive voltage, a method of generating negative high voltage from a single power source using a negative voltage boosting circuit is widely adopted.
A conventional example of such a negative voltage boosting circuit is disclosed in Japanese published unexamined patent application No. Hei 11-265593 and if the negative voltage boosting circuit disclosed in the patent application is described referring to FIGS. 9 to 11, FIG. 9 shows a circuit disclosed in the patent application, and FIG. 10 are a sectional view showing the structure of an N-type MOS transistor MN4 forming a boosting unit circuit CP4 and a wiring diagram showing connection relation among each terminal of the N-type MOS transistors MN4, P-type diffused layers 2 and 5 and N-type diffused layers 3 and 4.
FIG. 11 shows each signal waveform of clock signals for driving the negative voltage boosting circuit shown in FIG. 9, output voltage VPN from junction points A4, A5 and A41 and an output terminal Out, the channel current I1 of the N-type MOS transistor MN4, the base current I2 and the collector current I3 of a parasitic bipolar transistor.
The negative voltage boosting circuit shown in FIG. 9 includes a boosting unit circuit CP0 formed by an N-type MOS transistor MN0 the input terminal IN of which is connected to ground potential GND and five boosting unit circuits CP1 to CP5 formed by each combination of each N-type MOS transistor MN1 to MN5 and each N-type MOS transistor MN11 to MN51 and each combination of each capacitative element C1 to C5 and each capacitative element C11 to C51, and generates the output voltage VPN of the negative voltage boosting circuit at the output terminal Out of the last boosting unit circuit CP5.
Diodes D0 to D5 shown in FIG. 9 denote each parasiticdiode caused by a pn junction between a P-type well 8 in which each source and each drain of each N-type MOS transistor MN0 to MN5 are formed and an N-type well 9 in which the P-type well 8 is formed as shown in FIG. 10, and the N-type well 9 is biased by a power source Vcc respectively via the N-type diffused layers 1 and 6.
The N-type MOS transistors MN0 to MN 5 and the N-type MOS transistors MN11 to MN51 have the similar structure as a structural sectional view of the N-type MOS transistor MN4 is shown as an example in FIG. 10, and the source and the drain of each N-type MOS transistor are formed in the P-type well 8 separately from a P-type semiconductor substrate 10 so that the P-type well 8 is included in the N-type well 9 formed in the P-type semiconductor substrate 10.
The source of the N-type MOS transistor MN0 forming the boosting unit circuit CP0 is connected to the ground potential GND via an input terminal IN, the drain is connected in common to its own gate electrode and the P-type well 8 to be its own channel region and further, is connected to a junction point A1 which functions as an output terminal of the boosting unit circuit CP0.
In the boosting unit circuit CP1 connected next to the boosting unit circuit CP0, the source which functions as an input terminal of the N-type MOS transistor MN1 and the gate of the N-type MOS transistor MN11 are connected to the output terminal of the boosting unit circuit CP0, the drain of the N-type MOS transistor MN1 and the P-type well to be its own channel region are connected, further, the drain of the N-type MOS transistor MN11 and the P-type well to be a channel region of the N-type MOS transistor MN11 are connected in common and are connected to a junction point A2 which functions as an output terminal of the boosting unit circuit CP1.
One end of the capacitative element C1 is also connected to the junction point A1 which functions as the input terminal of the boosting unit circuit CP1 and a clock signal CK1 is applied to the other end of the capacitative element C1. One end of the capacitative element C11 is connected to the gate of the N-type MOS transistor MN1 and a clock signal CK3 is applied to the other end of the capacitative element C11.
The residual other boosting unit circuits CP2 to CP5 are also formed by the similar configuration, however, a clock signal supplied to the capacitative elements C1 to C5 and C11 to C15 is input so that the phase is reverse to the phase of the adjacent boosting unit circuit. That is, a clock signal CK1 and a clock signal CK2 are out of phase, and a clock signal CK3 and a clock signal CK4 are out of phase.
Next, the operation of the conventional type negative voltage boosting circuit shown in FIG. 9 will be described referring to FIG. 11.
FIG. 11 shows signal waveforms of voltage and current in case the vertical axis shows voltage or current and the horizontal axis shows time, and shows each signal waveform of clock signals CK1, CK2, CK3 and CK4, each voltage at the junction points A4, A5 and A41 and voltage VPN at the output terminal, the channel current of the N-type MOS transistor MN4, the base current I2 and the collector current I3 of a parasitic NPN transistor composed of the N-type diffused layer 3 which functions as an emitter, the P-type well 8 which functions as a base and the N-type well 9 which functions as a collector respectively shown in FIG. 10.
In the following operational explanation, to simplify the description, only the boosting unit circuit CP4 will be described in behalf of the other boosting unit circuits below. Before time t1, a clock signal CK2 is at a VCC level and at this time, electric potential at the junction point A4 is raised up to a level at which the N-type MOS transistor MN41 conducts via the capacitative element C4. When a clock signal CK1 becomes at a high level at time t2, electric potential at the junction point A5 is raised via the capacitative element C5. At this time, charge is supplied from an input terminal for a clock signal CK1 to be input to the junction point A41 via the N-type MOS transistor MN41 and electric potential at the junction point A41 of the gate of the N-type MOS transistor MN4 rises.
Next, at time t3, a clock signal CK2 becomes at a low level, negative pulse current flows to the junction point A4 via the capacitative element C4 and electric potential at the junction point A4 drops. At that time, a pn junction connected to the junction point A5 and the junction point A4 as shown in FIG. 10 is forward-biased, current I2 flows from the P-type diffused layers 2 and 5 to the N-type diffused layer 3, soon afterward, as positive pulse current flows to the gate of the N-type MOS transistor MN4 via the capacitative element C41 when a clock signal CK4 becomes at a high level at time t4, the gate potential of the N-type MOS transistor MN4 further rises, the N-type MOS transistor MN4 conducts enough and channel current I1 flows from the junction point A5 to the junction point A4. When this operation is sequentially repeated in each boosting unit circuit CP0 to CP5, the potential of output voltage VPN from the output terminal Out drops for example every cycle of a clock signal as shown in FIG. 11 and after predetermined time, the potential becomes negative fixed potential (−13 V).
In the above-mentioned conventional type negative voltage boosting circuit, when electric potential at the junction point A4 at the time t3 becomes lower than electric potential at the junction point A5, the P-type well 8 and the N-type diffused layer 3 are forward-biased and forward current I2 in the pn junction flows from the P-type diffused layers 2 and 5 to the N-type diffused layer 3 as base current as shown in FIG. 10. Therefore, collector current I3 acquired by multiplying the forward current I2 by a grounded emitter current amplification factor hfe flows from the N-type well 9 biased at VCC potential to the junction point A4.
Next, to continue the description referring to FIG. 12 showing voltage at the junction points of the conventional type negative voltage boosting circuit, channel current I1, the base current I2 and the collector current I3 of a parasitic NPN transistor, as the capacitative element connected to the junction point A4 is charged by the collector current I3 as shown at t3 and t4 in FIG. 12, electric potential which is to be dropped at the junction point A4 rises, voltage between the N-type diffused layer 4 (the drain) and the N-type diffused layer 3 (the source) decreases, therefore, channel current I1 which flows from the N-type diffused layer 4 (the drain) to the N-type diffused layer 3 (the source) decreases and boosting efficiency is deteriorated.
To explain more concretely, in case the grounded emitter current amplification factor hfe of the parasitic NPN transistor composed of the N-type diffused layer 3 which functions as an emitter and the N-type well 9 which function as a collector is small, the collector current I3 of the parasitic NPN transistor decreases as shown in FIG. 11. Therefore, as shown at t3 and t4 in FIG. 11, the rise of electric potential at the junction point A4 is reduced and large channel current I1 flows in the N-type MOS transistor MN4 as shown immediately after the time t4.
In the meantime, in case the grounded emitter current amplification factor hfe is large, the collector current I3 of the parasitic NPN transistor increases as shown in FIG. 12. Therefore, as shown at t3 and t4 in FIG. 12, the drop of electric potential at the junction point A4 is greatly reduced, compared with the variation shown in FIG. 11 of electric potential at the junction point A4, voltage between the N-type diffused layer 4 (the drain) and the N-type diffused layer 3 (the source) decreases, compared with that in case the grounded emitter current amplification factor hfe is small and channel current I1 which flows immediately after the time t4 in the N-type MOS transistor MN4 decreases.
The grounded emitter current amplification factor hfe greatly varies in the manufacturing process because base width Wb shown in FIG. 10 greatly varies in quantity production and in case the grounded emitter current amplification factor hfe is large, channel current I1 greatly decreases as described above.
As a result, as clear from relation between output voltage VPN and output current respectively shown in FIG. 13 from the negative voltage boosting circuit, a problem that no output current actually flows for the objective value −100 μA of output current when output voltage VPN from the conventional type negative voltage boosting circuit is −10 V occurs.
Therefore, the object of the invention is to provide a negative voltage boosting circuit the boosting efficiency of which is not deteriorated even if a grounded emitter current amplification factor hfe of a parasitic bipolar transistor is large.
Another object of the invention is to provide a negative voltage boosting circuit in which boosting unit circuits for boosting negative voltage are connected in series, the collector current of a bipolar transistor parasitic on a MOS transistor is reduced by connecting bias potential in a channel region of a MOS transistor for switching channel current between the output terminal of a boosting unit circuit and the input terminal of the boosting unit circuit to the output terminal of a boosting unit circuit closer to the output terminal of the negative voltage boosting circuit in place of connecting the above-mentioned bias potential to the drain (the output terminal) in the same channel region and the boosting efficiency is enhanced.
Further another object of the invention is to provide a negative voltage boosting circuit in which in a MOS transistor for transferring charge between an output terminal and an input terminal forming a boosting unit circuit close to the output terminal, applied voltage between each well biased by ground potential and the output terminal of each boosting unit circuit is reduced by turning the electric potential of each well including each channel region of these MOS transistors and forming a pn junction ground potential and which can boost more than withstand voltage even if the withstand voltage between each well including a channel region and forming a pn junction and the output terminal of each boosting unit circuit is short.